Liquid crystal display device

ABSTRACT

In a liquid crystal display device of the active matrix type using the in-plane switching (IPS) scheme with at least four transmission regions being formed within a single pixel area surrounded by neighboring gate wiring lines and neighboring drain wiring lines in a direction transverse to the drain wiring lines, the present invention makes use of a multilayer structure of two layers of conductive films with an insulating film sandwiched therebetween at a pixel electrode extending from either one of the neighboring gate wiring lines toward the pixel inside and causes one of these two-layer conductive films (i.e. lower pixel electrode placed on the substrate side) to bend or “crank” into a hook-like shape at a central portion of the pixel area while letting its planar shape be adjacent to one of the neighboring drain lines at the half of the pixel area and also letting it be adjacent to the other of the neighboring drain lines at the other half, thereby widening the viewing angle of an image to be visually displayed on the liquid crystal display device and also brightening the image.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to liquid crystal displaydevices and, more particularly, to liquid crystal display devices of theactive matrix type using thin-film transistor (TFT) schemes. Thisinvention also relates to manufacturing methods of the same.

[0003] 2. Description of Related Art

[0004] Liquid crystal display devices include in-plane switching (IPS)mode liquid crystal displays, which are designed to apply a lateralelectric field to a liquid crystal gap between upper and lowersubstrates with a layer of liquid crystal material interposedtherebetween. The IPS-mode liquid crystal displays are considered to bea display scheme capable of satisfying requirements for higher imagequality and have been experienced a variety of kinds of amelioration forfurther improvements in image quality.

[0005] In IPS-mode liquid crystal display (LCD) devices, a widely usedapproach is to employ the scheme for switching liquid crystals by use ofa lateral electric field to be created between two layers of metalelectrodes with an insulating film sandwiched therebetween. However,compared to display devices of the type using twisted nematic (TN)methods, this approach suffers from problems which follow: it isdifficult to enlarge the aperture ratio of picture elements or “pixels”;and, the light utilization efficiency stays lower in value. To avoidthese problems, a back-light unit used therein must be increased inluminance. This backlight luminance increase makes it difficult for anentire LCD module to achieve low power consumption such as required fornotebook personal computers (PCs) and handheld or “mobile” electronictools.

[0006] In order to solve this problem, an invention has been proposedsuch as disclosed, for example, in Published Unexamined Japanese PatentApplication No. 2002-98982.

[0007] Additionally, it is also known that active elements for liquidcrystal switching are configured from not only thin-film transistors(TFTs) with their channel regions (switching portions) made of amorphoussilicon (noncrystalline silicon) but also TFTs with channel regions madeof polysilicon (polycrystalline silicon).

SUMMARY OF THE INVENTION

[0008] IPS-type liquid crystal display devices are low in aperture ratioand thus are required to offer higher aperture ratio, that is, higheroptical transmissivity. Typically, pixels are designed to have acomb-like electrode structure using a single pixel electrode in an areathat is interposed between common electrodes—in other words, a structurewith each pixel bisected. However, the inventors' study has revealedthat structures with a pixel divided into more than four parts requirespecial designs for reducing display defects such as cross-talk while atthe same time further increasing the aperture ratio.

[0009] The present invention as disclosed herein provides an approach tosolve the newly found problems stated above, and an advantage of thisinvention is to further increase the aperture ratio while simultaneouslyreducing operation failure and crosstalk unique to an IPS display-modeliquid crystal display device which has a common electrode overlying adrain wiring line with an organic film laid therebetween and also has apixel electrode over the organic film while having more than four openregions that are surrounded by the common and pixel electrodes in across-sectional structure transverse to part between neighboring drainwiring lines.

[0010] These and other objects, features and advantages of the presentinvention will be apparent from the following more particulardescription of preferred embodiments of the invention.

[0011] Some major means for attaining the object in accordance with thisinvention are as follows.

[0012] (1) In an active matrix type liquid crystal display device havinga first substrate and a second substrate which are disposed to face eachother with a liquid crystal layer interposed therebetween and havingabove the first substrate a plurality of gate wiring lines and aplurality of drain wiring lines crossing the plurality of gate wiringlines in a matrix form and also thin-film transistors formed in a waycorresponding to respective cross points of the gate wiring lines andthe drain wiring lines, with a pixel being constituted from an area assurrounded by neighboring gate wiring lines and neighboring drain wiringlines, the device is arranged in a way which follows: a plurality ofpixel electrodes are provided, at least two pixel electrodes thereofhave a first area that is a linear portion constituted from two layersof upper and lower layers with an insulating film sandwichedtherebetween and a second area that is a linear portion provided only atan upper portion of the insulating film; the two pixel electrodes aredifferent from each other in order of the first area and second area ofthe pixel electrodes; and, portions formed at a lower layer of theinsulating film making up the first area are connected to each other atthe two pixel electrodes.

[0013] (2) The distance between one pixel electrode of the two pixelelectrodes and one of two drain wiring lines disposed on the both sidesof a pixel is selected to be greater than twice the distance relative tothe remaining drain wiring line, whereas the distance between theremaining one of the two pixel electrodes and the remaining drain wiringline of the two drain wiring lines disposed on the both sides of thepixel is greater than twice the distance relative to the one drainwiring line.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a plan view of main part of a pixel of a TFT liquidcrystal display device in accordance with one embodiment of the presentinvention;

[0015]FIG. 2 is a cross-sectional view of main part of the pixel astaken along line 2-2′ of FIG. 1 which is the TFT liquid crystal displaydevice in accordance with one embodiment of this invention;

[0016]FIG. 3 is a sectional view of main part of the pixel taken alongline 3-3′ of FIG. 1 which is the TFT liquid crystal display device inaccordance with one embodiment of the invention;

[0017]FIG. 4 is a sectional view of main part of the pixel along line4-4′ of FIG. 1 which is the TFT liquid crystal display device inaccordance with one embodiment of the invention;

[0018]FIG. 5 is a diagram for explanation of a relationship of apolarization plate versus an initial orientation direction in accordancewith one embodiment of the invention;

[0019]FIG. 6 is a plan view schematically representing an equivalentcircuit of the TFT-LCD;

[0020]FIG. 7 is a timing chart showing a drive waveform of a pixel ofthe TFT-LCD;

[0021]FIG. 8 is a plan view of a pixel of a TFT liquid crystal displaydevice in accordance with another embodiment of the invention; and

[0022]FIG. 9 is a sectional view of main part along line 9-9′ of FIG. 8in another embodiment of the invention.

DETAILED DESCRIPTION

[0023] Representative structures incorporating the principal features ofthis invention will be explained in conjunction with illustrativeembodiments below.

[0024] <Embodiment 1>

[0025]FIG. 1 depicts a plan view of one of pixels (picture elements)provided for a liquid crystal display device in accordance with oneembodiment of the invention, and FIGS. 2 through 4 are cross-sectionalviews of the pixel of FIG. 1 as taken along dash-dot cut lines 2-2′,3-3′ and 4-4′, respectively. In these drawings, the numerals indicativeof cut portions are encircled for purposes of providing visual emphasisof the cut portions. Note that these drawings are the ones that indicatemain part for explanation purposes and that orientation films areeliminated from some of the drawings. Also note that a structure on theopposite or “counter” substrate side also is eliminated in some drawingsfor purposes of convenience in illustration only. Details will be setforth one by one below.

[0026]FIG. 1 shows a schematic planar pattern of the one of the pixels.This one of the pixels is arranged to be surrounded by neighboring gatewiring lines GL and neighboring drain wiring lines DL. A gate wiringline GL also functions as the gate electrode of a thin-film transistor(TFT) with its semiconductor layer made of polysilicon (poly-crystallinesilicon) PSI, for supplying a voltage which drives the TFT to turn onand off. For instance, a current supplied to a polysilicon PSI (shownlower-left in FIG. 1) from a drain line DL shown left in FIG. 1 (one ofthe neighboring drain wiring lines) is supplied to liquid crystalcapacitance and hold capacitance (charge-holding capacitance helping theliquid crystal capacitance hold charge thereby) in the one of the pixelto apply an image voltage (drain voltage) to each of the capacitance atthe timing at which one of the neighboring gate wiring lines GL (shownat lower side of FIG. 1) applies the turn-on voltage to the polysiliconPSI. Consequently, a metal pixel electrode SPM (connected to thelow-temperature polysilicon PSI) as extended up to a central portion ofthe pixel and a transparent pixel electrode SPT coupled thereto becomeequal in potential to the image voltage.

[0027] The current is expected to flow from the drain wiring line DLthrough a first contact hole CNT1 into the polysilicon PSI. A current inthis polysilicon flows into the metal pixel electrode SPM through asecond contact hole CNT2. The metal pixel electrode SPM extends beneaththe transparent pixel electrode SPT up to a central portion of the pixelat which the drain wiring line DL and transparent pixel electrode SPTare bent and then curves at this portion in a direction substantiallyperpendicular to the elongate direction of the drain wiring line andnext extends across a transparent common electrode CLT and thereafter,at a portion under another transparent electrode SPT, again extendsbeneath the another transparent electrode SPT toward another of theneighboring gate wiring lines GL (shown at upper side of FIG. 1).

[0028] Since the another of the neighboring gate wiring lines GLcontributes to operation of another of the pixels adjacent (in anextension direction of the drain wiring line DL) to the one of thepixels (as FIG. 1 shows mainly) which the one of the neighboring gatewiring lines GL contributes to operation of, the another of theneighboring gate wiring lines GL is denoted as “a gate wiring line ofthe prior stage” hereinafter. This denotation is based on the assumptionthat the another of the pixels (partially shown in upper side of FIG. 1)is scanned prior to the one of the pixels, and if the another of thepixels is scanned next to the one of the pixels, the gate wiring line ofthe prior stage is renamed “a gate wiring line of the next stage”. Onthe other hand, the one of the neighboring gate wiring lines GL scanningthe one of the pixels (i.e. a pixel mainly exemplified in an explanationof an embodiment) is denoted as “a gate wiring line of the presentstage”, also. However, scanning sequence of the one of the pixels andthe another of the pixels is not limited in this embodiment.

[0029] Then as shown in the upper side of FIG. 1, the metal pixelelectrode SPM forms the hold capacitance together with the gate wiringline GL of the prior stage (the prior stage gate wiring line,hereinafter) and reaches a transparent electrode SPT overlying aninsulating film through a third contact hole CNT3 at this position. Thetransparent electrode SPT is laid out to have a Japanese KATAKANA letter“ko”-like or “U”-like planar shape, by way of example.

[0030] A common electrode potential of another electrode that makes upthe liquid crystal capacitance together with the pixel electrode isapplied along a route or path which follows. The transparent commonelectrode wiring line CLT is disposed in such a way as to shield theabove-noted wiring line at its upper part via an insulating film of lowdielectric constant above the gate and drain wiring lines GL and DL. Thetransparent common electrode wiring line CLT is branched into the pixelinside to thereby function as the common electrode that drives liquidcrystals together with the pixel electrode SPT. In this way, thetransparent common electrode wiring line CLT is laid out to have amesh-like pattern in such a manner as to cover or coat the gate anddrain wiring lines GL and DL and is connected and tied to alow-resistance wiring line made of a metal in a display screenperipheral area. This low-resistance wiring line is the one that acts asa bus line with a common potential.

[0031] In the IPS liquid crystal display device, the value defined by alateral electric field between the transparent common electrode CLT andthe transparent pixel electrode SPT of FIG. 1 is a liquid crystalcapacitance so that this value is less than or equal to half of that inliquid crystal display devices of the type using vertical electric fieldmethods such as the TN scheme which defines the liquid crystalcapacitance between electrodes disposed on upper and lower opposingsubstrates respectively. Due to this, only in the lateral electric fieldscheme having both the common electrode and the pixel electrode on onesubstrate, the wiring-line resistance specification of the transparentcommon electrode wiring line CLT may offer the capability to lessen awiring line delay even when using transparent electrode material withincreased resistance values to thereby make it possible to obtain higherimage quality. Obviously any available transparent electrode materialsare employable, including but not limited to indium-zinc-oxide (IZO) andindium-tin-zinc oxide (ITZO).

[0032] Voltage potentials of this common electrode and the commonelectrode wiring line are such that an almost mid-point potential of thepixel potential is set which is changed into an AC form in units offrames by way of example (as will be explained in detail again in FIG.7). These pixel electrode potential and common electrode potentialconstitute the liquid crystal capacitance and, simultaneously, adifference between these potentials is used to create an electric fieldwithin the liquid crystal layer, causing an image to be visuallydisplayed by use of the common voltage and an image voltage as suppliedfrom the drain wiring line DL. On the other hand, a potential of thehold capacitance is formed between the pixel electrode potential and aprior stage gate wiring line with the gate wiring line (of the presentstage) scanned. After the potential of the prior stage gate wiring linewas scanned, the potential of gate wiring line is kept at a stabilizedconstant potential level during scanning of a gate wiring line of a TFTthat drives a corresponding pixel and thus becomes an electrode thatmakes up the hold capacitance.

[0033] One of the principal features of this embodiment lies in theplanar pattern of the metal pixel electrode SPM within a single pixelarea. The metal pixel electrode SPM functions to transmit the pixelpotential that was sent through the second contact hole CNT2 to a thirdcontact hole CNT3 transmitting toward the transparent pixel electrodeSPT at a portion over the gate wiring line GL. If aimed only attransmission of the voltage of the pixel potential, the metal pixelelectrode SPM may be arranged in layout so that only the lower part ofthe transparent pixel electrode SPT nearest to a drain wiring line DL onthe left hand side of FIG. 1 is disposed with the shortest distance tothe prior stage gate wiring line GL. However, the metal pixel electrodeSPM of this embodiment is specifically disposed so that at almostcentral portion of the transmission area between the neighboring gatewiring lines GL, it extends beneath the transparent pixel electrode SPTwhich is nearest to the drain wiring line DL on the left hand in thedrawing sheet to reach the pixel center and then curves at a locationnear the center to a direction substantially perpendicular to the drainwiring lines and thereafter extends under the transparent pixelelectrode SPT that is nearest to a drain wiring line DL on the righthand of the drawing sheet to reach the prior stage gate wiring line GL.As apparent from FIG. 1, this is a very characteristic pattern. Thispattern is a layout that permits the distances from the drain wiringlines DL to the metal pixel electrode SPM to become substantiallysymmetrical with respect to the mutual drain wiring lines within asingle pixel. With such an arrangement, it becomes possible to reducethe particular phenomenon such as operation failure or crosstalkotherwise occurring due to unwanted potential variations of the drainvoltage as found by the inventors of this patent application to be laterdescribed in detail in FIGS. 2 and 3. At this time, with the use of thestructure with the metal pixel electrode SPM being curved within a onepixel to provide an almost symmetrical layout pattern within the onepixel, it is possible to cause the capacitance being formed between theupper-side transparent pixel electrode SPT and the metal pixel electrodeSPM to be substantially equal with respect to two pixel electrodes SPT.This in turn makes it possible to further stabilize the holdcharacteristics.

[0034] Furthermore, since the two transparent pixel electrodes SPT aresuch that the capacitance is formed between each and the metal pixelelectrode SPM, the pixel potential is supplied by this capacitance also.Due to this, even when the transparent pixel electrode SPT iselectrically disconnected or “open-circuited” at its portion, theintended pixel potential supplement is still achievable by thiscapacitance, thus enabling performance of proper display operations. Inthis way, it is possible to arrange a liquid crystal display devicewhich is less in occurrence of dot defects and is very high inmanufacturing yields. This can be said because any accidental electricaldisconnection of the gate wiring lines GL and drain wiring lines DL iscorrectable and repairable in TFT processes. In addition, as the commonpotential is supplied by the transparent common electrode CLT in amatrix form, the influence of such disconnection will no longerstructurally occur. And, electrical shorting is correctable even afterproduct completion by cutting and separating a shorted portion(s) usinga laser, for example. Although only the difficulty in such repair wasdot defects occurring due to pixel electrode disconnection, the use ofthis structure makes it possible to avoid this problem also because ofits capability to retain display owing to capacitive coupling. Thus itis possible to realize extremely high production yield. And in thiscase, the yield is further improved by designing the metal pixelelectrode SPM so that this is made of a metal and is located beneath thetransparent pixel electrode associated therewith. More specifically, themetal electrode is higher in micromachining accuracy than transparentelectrodes made of indium-tin-oxide (ITO) or the like while at the sametime offering a finer line and enhanced electrical disconnectionpreventability. Furthermore, although one cause for disconnection ofmetal wiring lines is infiltration of etching liquids at the time ofmicromachining at later process steps, disposing the metal pixelelectrode SPM on the lower side of the transparent pixel electrode SPTresults in achievement of a structure with the underlying metal pixelelectrode SPM being protected by its overlying transparent pixelelectrode SPT during the etching processes. Thus it becomes possible tofurther improve the disconnection preventability, thereby enablingrealization of further improvements in yields.

[0035] Further note that the position at which the metal pixel electrodeSPM curves is disposed along a transversal area which couples thosepoints at which the drain wiring lines DL and transparent commonelectrode CLT plus transparent pixel electrode SPT are bent. Thiscurvature is for change of the direction of an electric field betweenthe upper half part and lower half part of such planar pattern with thisposition as a boundary to thereby preclude gradation or gray scalereversal when looking at from a specific direction. Accordingly, thearea that couples these curve points is inherently a region in whichdisplay-use optical elements change in light distribution direction andthus liquid crystal molecules are difficult to be well controlled;therefore, the area does not contribute to optical transmission in anyway. Consequently, even when the metal pixel electrode SPM extendsacross this area, the transmissivity hardly decreases as far as theelectrode is narrow in width, thereby enabling provision of the intendedliquid crystal display device with increased aperture ratios andenhanced brightness. The metal pixel electrode SPM is a wiring linewithin a single pixel and is not expected to have any role for powerfeed of the entire display screen unlike the gate wiring lines GL anddrain wiring lines DL whereby currently established minimum feature sizerules are usable so that the line may be made narrower than theindividual gate wiring line GL to thereby enable achievement of furtherimprovements in aperture ratio. Additionally the line may also be madenarrower than the individual drain wiring line DL. In this case theaperture ratio is further improved.

[0036]FIG. 2 is a sectional view of the pixel as taken along line 2-2′of FIG. 1, which is a portion that extends across a one pixel areabetween neighboring drain lines DL. An underlayer insulating film ULSwhich is structured from an Si₃N₄ film with a thickness of 50 nanometers(nm) and an SiO₂ film with a thickness of 120 nm is formed on anon-alkali TFT glass substrate GLS1 with its distortion point of about670° C. The underlayer insulating film ULS functions to prevent unwanteddiffusion of an impurity such as Na or the like from the TFT glasssubstrate GLS1. On the underlayer insulating film ULS, a gate insulationfilm GI made of SiO₂ is formed. Disposed on the gate insulator film is alow-temperature polysilicon PSI for supplying a pixel potential.

[0037] An interlayer dielectric film ILI made of SiO₂ is formed to coverthe above-mentioned structure. Drain wiring lines DL are formed on theinterlayer dielectric film ILI, wherein each drain wiring line DL has athree-layer metal film structure of Ti/Al/Ti. The metal pixel electrodeSPM is formed by the same process and the same material as those of thedrain wiring lines DL.

[0038] The layer is covered with two films as formed thereon, one ofwhich is a dielectric protective film PAS made of Si₃N₄ with a thicknessof 200 nm and an organic protective film FPAS with a thickness of 2micrometers (μm), wherein the latter is mainly comprised of acrylicresin material. On the organic protective film FPAS, a transparentcommon electrode wiring line CLT made of indium-tin-oxide (ITO) is firstformed to have a width greater than that of drain wiring line DL. Atransparent pixel electrode SPT that is made of ITO and fabricated bythe same process and the same material is also formed on the organicdielectric film FPAS.

[0039] The wiring line materials in the explanation above are mereexemplary and should not be interpreted as the ones that limit the scopeof the invention.

[0040] Some major optical transmission regions are four areas whichfollow: (1) an area between the transparent common electrode CLToverlying a drain line DL and a transparent pixel electrode SPT that isdisposed to cover the metal pixel electrode SPM on the left hand side ofthe plan view of FIG. 1, (2) an area between the transparent pixelelectrode SPT and a transparent common electrode CLT that extends upwardfrom the upper side of gate wiring line GL, (3) an area between thetransparent common electrode CLT and a transparent pixel electrode SPT,and (4) an area between the transparent pixel electrode SPT and atransparent common electrode wiring line CLT overlying a drain wiringline DL. The transparent pixel electrode SPT and the transparent commonelectrode CLT are the electrodes which drive liquid crystals.

[0041] On the other hand, an opposite substrate for sealing a liquidcrystal material LS is a color filter (CF) substrate GLS2. This CF glasssubstrate GLS2 is such that color filters (FIL) made of organic materialwith color-displaying pigments being scattered on the liquid crystalside become color filters which represent transmission light rays ofblue (B), red (R) and green (G) in accordance with those colors asassigned on a pixel basis—for example, “FIL(R)” for red. On the innerside thereof, an overcoat film OC which is made of organic material isformed. Although the OC film may be eliminated, it is desirable thatthis film be used for planarity improvement purposes. An orientationfilm OLI is printed on the surfaces of CF substrate GLS2 and TFTsubstrate GLS1 which are in contact with the liquid crystals LC withrubbing applied thereto to thereby control the initial orientation oralignment direction(s). In addition, polarization plates POL are pastedto outside surfaces of the CF glass substrate GLS2 and TFT glasssubstrate GLS1. These polarizers POL are designed to provide what iscalled the “cross nicol” state with deflection axes being crossedtogether at right angles between the opposite glass substrates.

[0042] An angular relationship of the rubbing direction and thepolarizer is shown in FIG. 5. One polarized light axis PD2 is in thesame direction as GL, while the other polarized light axis PD1 is in anorthogonal direction to GL. Additionally the rubbing direction RD in theupper and lower substrates is set in a direction orthogonal to GL. Withsuch an arrangement, the so-called “normally black” mode layout isprovided; further, with the pixel pattern with the curved shape such asshown in FIG. 1, multi-domain design is achieved. Obviously the case ofanti-multi-domain also is involved within the scope of the presentinvention: in such case also, it is required that the polarizer layoutpermit establishment of the cross nicol state.

[0043] The so-called black matrix BM is not formed at the CF substrateGLS2 in this cross-section. Combining the colors of the color filter FILis done above transparent common electrode wiring lines CLT which aredisposed to cover or coat the drain wiring lines DL.

[0044] Desirably the transparent common electrode wiring lines CLTcoating the drain wiring lines DL are designed so that the width of eachwiring line CLT is selected to be more than two times larger than thewidth of a drain wiring line DL. This is required in order to achievethe shielding of a drain potential to thereby preclude the risk ofoperation failure or malfunction of the IPS liquid crystal displaydevice otherwise occurring basically due to application of electricfields other than a common electrode potential and a pixel potential tothe liquid crystals. Also note that in IPS liquid crystal displaydevices using positive-type liquid crystal materials, no light raystransmit and penetrate on the inner side thereof even at portions overtransparent electrodes. This is because any lateral electric fields areapplied over widened electrodes resulting in liquid crystal moleculesbeing prevented to rotate in any way. However, in a region of about 1.5μm as measured from an end portion of transparent electrode toward itsinside along the width, a fringe-like lateral electric field is appliedpermitting transmission of light rays.

[0045] For the liquid crystals LC, electric fields being applied to thetransparent pixel electrode SPT and transparent common electrode CLT areused to drive the liquid crystals. As previously stated, the electricfield created by an image voltage in the event that the drain wiringline DL drives those pixels other than a target one is such that theorganic protective film FPAS is thickened while designing its overlyingtransparent common electrode CLT to have an increased width whereby suchelectric field component will no longer leak into the liquid crystals LSso that any operation failure of images does no longer occur due to thiselectric field. In this way, the influence stays less upon the part thatspans from the drain wiring line DL to the upper part in the sectionalstructure of FIG. 2—that is, the liquid crystal LC side.

[0046] However, an electric field that extends from the drain wiringline DL to the TFT glass substrate GLS1 can indirectly cause operationfailure of image quality. The TFT glass substrate GLS1 is mainlycomprised of SiO₂ with its relative dielectric constant of 4. However,unlike quartz crystals, it contains as an impurity a high relativedielectric constant material such as alumina so that the resultingrelative dielectric constant is as high as 6 to 7. On the other hand,the organic protective film is made of acrylic resin with a relativedielectric constant of 3 and with its thickness being as large as 2 μm.Accordingly, the influence of an electric field (Cds1 in FIG. 2) thatpenetrates the TFT glass substrate GLS1 from the left hand side drainwiring line DL in FIG. 2 to a portion between neighboring metal pixelelectrodes SPM becomes larger due to the presence of a difference inrelative dielectric constant between the organic protective film and theTFT glass substrate. Obviously the influence of an electric field (Cds2in FIG. 2) passing through the TFT glass substrate GLS1 from the righthand side drain wiring line DL in the drawing to the metal pixelelectrode SPM becomes smaller because Cds2 is greater than Cds1 indistance between the drain wiring line and metal pixel electrode SPM.More specifically, asymmetry occurs with respect to two drain wiringlines DL. Due to this, a signal being held by the TFT of a pixel by adisplay image of one drain wiring line can often be affected by thecapacitive coupling, resulting in the risk of display image turbulence.

[0047] To avoid the risk, with this invention, the metal pixel electrodeSPM is specifically laid out so that it curves within a pixel as shownin FIG. 1 to thereby eliminate this asymmetry.

[0048]FIG. 3 is a cross-sectional view as taken along line 3-3′ ofFIG. 1. The cross-section shown herein is a profile which extends acrossneighboring drain wiring lines of an upper half pixel part, wherein themetal pixel electrode SPM that is extended from the second contact holeCNT2 in the pixel plan view of FIG. 1 curves at a location near thecenter of the display screen and again extends toward the prior stage ofgate wiring line GL in a direction almost parallel to the drain wiringline DL. Although the structure above the TFT glass substrate GLS1 issubstantially the same as that in the cross-section of FIG. 2, adifference therebetween lies in layout of the metal pixel electrode SPM.The metal pixel electrode SPM is disposed on the interlayer dielectricfilm ILI with its upper portion covered by the protective film PAS andorganic protective film FPAS. Further at its upper portion, thetransparent pixel electrode SPT is disposed to cover the metal pixelelectrode SPM. While the layout of the cross-sectional structure is thesame as that of the structure of FIG. 2, a difference is as follows:whereas in the structure as shown in FIG. 2 the metal pixel electrodeSPM is laid out at lower part of the transparent pixel electrode SPTadjacent to the left hand side drain wiring line in the drawing, thestructure as shown in FIG. 3 is such that it is disposed at lower partof the transparent pixel electrode SPT adjacent to the right hand sidedrain wiring line DL in the drawing. With this design, in the structureas shown in FIG. 3, the influence Cds2 of an electric field from theright hand side drain wiring line DL in the drawing through the TFTglass substrate GLS1 becomes greater than the influence Cds1 from theleft hand side drain wiring line DL in the drawing.

[0049] This results in achievement of a structure in which the electricfield influence in the planar structure of FIG. 1 through the TFT glasssubstrate GLS1 on the metal pixel electrode SPM is such that in the planview of FIG. 1 the metal pixel electrode SPM strongly receives theinfluence of the left hand side drain wiring line DL in a lower halfarea in the drawing and receives the influence of an electric field ofthe right hand side drain wiring line DL in an upper half area in thedrawing. Thus it is possible to set so that the influence from theneighboring drain wiring lines DL becomes symmetrical with respect tothe whole metal pixel electrode SPM.

[0050] The above-stated structure offers an advantage which follows: inthe case of implementing a dot inversion drive method which is a drivemethod of the TFT liquid crystal display device for achievement of thestate with polarity-different voltages are applied to the neighboringdrain wiring lines, crosstalk due to potential variations thereof may bereduced. More specifically, in case a constant voltage with the positivepolarity is applied from FIG. 1 to the left hand side of FIG. 3 while avoltage with the negative polarity is applied to the right hand sidedrain wiring line DL, the metal pixel electrode SPM will no longer varyin potential because potential variations thereof is such that thedistance of from the metal pixel electrode SPM up to the drain wiringline DL always stays the same in average within a one pixel area betweenneighboring gate wiring lines. Whereby, the transparent pixel electrodeSPT as connected thereto also hardly varies in potential, resulting inprevention of any appreciable crosstalk generation.

[0051] Another method for retaining the symmetry of potential variationis available, which employs a scheme for disposing the metal pixelelectrode SPM at the entire lower part of two transparent pixelelectrodes SPT adjacent to the drain wiring lines DL of FIGS. 2 and 3.Obviously the use of this scheme also makes it possible to achievepreclusion of the crosstalk stated above, although this would sometimesresult in a decrease in optical transmissivity—namely, aperture ratioreduction—due to the fact that the metal pixel electrode SPM and thetransparent pixel electrode SPT are incapable of being thinner than theminimum micromachine line width. However, the transparent pixelelectrode SPT and transparent common electrode CLT are such that theirportions spanning from the end portion thereof up to the electrodeinside of 1.5 μm contribute to the transmission under the influence of afringe electric field(s). Accordingly, in order to increase the apertureratio in the IPS display device using such transparent pixel electrodeand transparent common electrode, it is effective to minimize theembedment of an opaque metal and low transmissivity semiconductormaterial at lower portions of the electrodes. Owing to this, thestructure with the lower-layer metal pixel electrode SPM curving withina one pixel area in the way described in detail with reference to FIG. 1and others is capable of providing a liquid crystal display device withhigh in aperture ratio while suppressing crosstalk. Also note that thepixel center of FIG. 1 at which the metal pixel electrode SPM curves isan area in which each electrode curves and also an area in which liquidcrystal molecules mutually invert and thus no light inherentlypenetrates irrespective of whether the metal pixel electrode is presentor absent so that the aperture ratio is not newly lowered by thepresence of such curved metal electrodes.

[0052]FIG. 4 is a cross-sectional view taken along line 4-4′ of FIG. 1.This sectional view shows a cross-section of a portion of FIG. 1 whichleads to a storage capacitance along the metal pixel electrode connectedto a TFT of low-temperature polysilicon PSI. The left side of thesectional view of FIG. 4 is a cross-section of the TFT. A metal oxidesemiconductor (MOS) TFT is structured with the drain wiring line DL andmetal pixel electrode SPM as its drain electrode and source electrodeand also with the gate wiring line GL as its gate electrode, which iselectrically insulated by a gate insulation film GI. A polysilicon layerPSI is over ULS. The drain wiring line DL is connected via the firstcontact hole CNT1 as defined in the gate insulation film GI andinterlayer dielectric film ILI to a heavily-doped n type layer PSI(n+)with phosphorus of the low-temperature polysilicon PSI doped therein asan impurity. This heavily-doped n-type layer PSI(n+) is high inelectrical conductivity and thus virtually acts as a wiring portion. Onthe other hand, PSI under GL is a p-type layer PSI(p) with boron dopedthereinto as an impurity and acts as the so-called semiconductor layerwhich exhibits switching operation in such a way that it is in aconductive state when an ON voltage is applied to GL and in anon-conductive state upon application of an OFF voltage thereto. In casethe ON voltage is applied to the gate wiring line GL, the potential ofan interface between the gate insulation film GI and the boronimpurity-doped p-type layer PSI(p) at the lower part of the gateinsulator film GI at lower part of the gate wiring line GL is invertedresulting in formation of a channel region, followed by transformationto n conductivity type to permit an ON current to flow in the TFT. Thisin turn results in flow of a current into the metal pixel electrode SPMto thereby charge up the liquid crystal capacitance and holdcapacitance.

[0053] As shown in FIG. 4 the hold capacitance (called the additionalcapacitance, also) Cadd is formed with the metal pixel electrode SPM asits one electrode, with the interlayer dielectric film ILI as itsinsulating film, and with the prior stage gate wiring line GL as itsother electrode. The metal pixel electrode SPM overlying the prior gatewiring line GL supplies a pixel voltage potential to the transparentpixel electrode SPT through a third contact hole CNT3 that is defined inthe protective film PAS and organic protective film FPAS. While thismetal pixel electrode SPM crosses or intersects the transparent commonelectrode CLT in its crank-like curved area of FIG. 1, this electrodecrosses lower part of the organic protective film FPAS underlying thetransparent common electrode CLT as shown in FIG. 4 as far as thecross-sectional structure is concerned.

[0054] The hold capacitance Cadd is provided to retain the potentialwithin an image display time period (hold period) which is determined bythe liquid crystal capacitance with respect to a leakage current thatincreases due to electron-hole pairs as produced by light irradiationowing to a display-use backlight from the TFT glass substrate GLS1 sidewith respect to the polysilicon PSI of the TFT of the drawing. If thisvalue can be set larger, then it is possible to successfully retain theuniformness on the display screen.

[0055] An equivalent circuit of a display matrix unit and its peripheralcircuit are shown in FIG. 6 in circuit diagram form. In this drawing, DLdesignates drain lines suffixed with numbers in a manner of DL1, DL2,DL3, etc. These numbers indicate drain wiring lines (image signal lines)within the display screen as counted up from the left side of thescreen. Suffixes R, G and B are added in a way corresponding to red,green and blue pixels respectively. GL denotes gate wiring lines GL withnumbers added in a manner of GL1, GL2, GL3, etc. These numbers indicategate lines within the display screen as counted up from upper partthereof. Suffixes 1, 2, . . . are added in accordance with the sequenceof scan timings. CLX and CLY mean common electrode wiring lines CLT,wherein CLXs are suffixed with numbers in a manner of CLX1, CLX2, etc.These numbers indicate common electrode wiring lines within the displayscreen in the lateral direction as counted up from the upper partthereof. On the other hand, CLY denotes common electrode wiring lines inthe longitudinal direction, which are added numbers in a manner of CLY1,CLY2, etc. These numbers indicate the longitudinally extending commonelectrode wiring lines within the display screen as counted up from thescreen upper part. Although the above-noted common electrode wiringlines CLX, CLY are numbered as far as the equivalent circuit isconcerned, actually these are transparent common electrodes CLT as shownin FIG. 1 while letting CLX covering more than one gate wiring line endportion with CLY being a transparent electrode that covers a drainwiring line(s) DL and are laid out in a mesh-like form. Then, these areconnected to a common electrode mother line CBL outside the displayscreen.

[0056] The gate wiring lines GL (suffixes omitted) are coupled to ascanning circuit GSCL on a glass substrate. Either a power supplyvoltage or a timing signal being given to such a scan circuit issupplied from a power supply and timing circuit SCC, which is formed ona PCB outside the glass substrate. Although in the above configurationthe scan circuit on the glass substrate which is constituted fromlow-temperature polysilicon TFTs is electrically powered also from theright side GSLR of the right and left side ones with respect to a singlegate line (scan line) in order to enhance redundancy, power supply mayalternatively be done from one side in accordance with display screensizes.

[0057] On the other hand, power feed is done to the drain wiring linesDL from a signal circuit DDC that is constituted from low-temperaturepolysilicon TFTs on the glass substrate. This signal circuit DDCfunctions to distribute image data incoming from circuitry formed ofimage signal circuit ICs on the glass substrate in response to colordata of R, G and B. Thus the number of connection nodes from the signalcircuit on the glass substrate is one third of the number of the drainwiring lines within the display screen.

[0058] Additionally the common electrode wiring line is the transparentcommon electrode wiring line CLT in this embodiment.

[0059] This common wiring line is tied within the mesh-like pixel asshown in FIG. 1. CLX and CLY are drawn out to the right and left of thedisplay screen or alternatively in upward and downward directions andare tied together to the common electrode mother line CBL which is lowin impedance and then connected to SCC of the power supply and timingcircuit IC. This common electrode gives a common potential of pixelswithin the display screen.

[0060] The low-temperature polysilicon TFTs within the screen are n-typeTFTs, each of which performs visual display by supplying a liquidcrystal capacitance CIc between it and a common electrode wiring lineCLT with a drain voltage (data) which is fed to a drain line DL at thetiming of application of a gate voltage to a gate wiring line GL. Inorder to improve the ability to retain the potential of the liquidcrystal capacitance CIc within a display period, a hold capacitance Caddis formed. CC is a test circuit that is formed of more than onelow-temperature polysilicon TFT for testing electrical disconnection ofdrain wiring lines DL. CPAD is a test terminal.

[0061]FIG. 7 shows a drive signal waveform of the liquid crystal displaydevice of this invention. Shown herein is an example in case a commonelectrode voltage Vcom is a DC voltage. A gate voltage Vg sequentiallyscans on a gate line basis whereby a pixel TFT becomes in a turn-on (ON)state upon application of a voltage which is obtained by further addingthe threshold voltage of the pixel's low-temperature polysilicon TFT toa drain potential Vd, resulting in chargeup to the liquid crystalcapacitance CIc shown in FIG. 6. The common electrode voltage Vcom, gatevoltage Vg and drain voltage Vg are applied to the common electrodewiring line CLT for making up the mesh-like common electrode wiringlines of FIG. 6, the gate wiring line GL and the drain wiring line DL,respectively. In this embodiment the drain voltage Vd is shown in thecase of performing white display during liquid crystal displaying in anormally black mode, by way of example, wherein gate line selection isdone on a line basis with inversion between positive and negativepolarities being done for the common electrode voltage Vcom once at atime whenever a line is selected. Although a pixel potential Vp ischarged up to the liquid crystal capacitance CIc through a TFT, it willbe inverted relative to the common electrode potential Vcom inodd-numbered and even-numbered frames. While the potential correspondingto an image is charged to the liquid crystal capacitance CIc when Vgbecomes greater than Vd upon selection of a gate wiring line withrespect to the gate wiring line GL of a TFT at a specific address, thepotential of liquid crystal capacitance CIc must be retained untilapplication of Vd that was inverted relative to the common electrodepotential Vcom in the next frame in the way stated above. This retentionrate decreases with an increase in a turn-off current (leakage current)of the TFT. To avoid this, it is required to enlarge the holdcapacitance Cadd of the equivalent circuit of FIG. 6.

[0062] In this embodiment a dot inversion drive method is used. In thiscase, supposing that the drive signal waveform for the TFT that isconnected to the drain wiring line DL1 of FIG. 6 is the same as thatshown in FIG. 7, the drain voltage Vd is inverted with regard to the TFTthat is connected to the drain wiring line DL2 of FIG. 6. Morespecifically, in case a gate is selected (when Vg becomes higher thanthe common voltage Vcom), in case the drain voltage Vd is higher thanthe common voltage Vcom, the neighboring drain wiring line DL2 isapplied the drain voltage Vd with its potential lower than that of thecommon voltage Vcom—that is, a voltage which is the same as that in aneven-numbered frame with respect to the drain wiring line DL1.Accordingly, a pixel placed between the drain wiring line DL1 and drainwiring line DL2 is surrounded by a voltage of a different polarity andthe same value; however, in this case, malfunction of the potential willno longer occur due to the fact that the crank-like curved metal pixelelectrode SPM is laid out as shown in FIG. 1.

[0063] <Embodiment 2>

[0064]FIG. 8 is a plan view of a pixel in accordance with a secondembodiment of the invention. FIG. 9 shows a cross-section of the pixelas taken long a cut line indicated by dash-dot line 9-9′ in FIG. 8. Inthese drawings, reference numerals are encircled in order to facilitatean understanding of the cut portion. In addition, reference charactersof the upper and lower gate wiring lines GL and right and left drainwiring lines DL which surround a single pixel are added with suffixnumerals for purposes of making clearer their scanning orders and thelike.

[0065]FIG. 8 is an IPS scheme pixel pattern having four maintransmitting portions in a direction transverse to the drain wiringlines DL in a way similar to the embodiment 1. Its significant featureover the embodiment 1 lies in a configuration which follows. A singlepixel area which is surrounded by two neighboring gate wiring lines GL1,GL2 and two neighboring drain wiring lines DL1, DL2 is designed so thata hold capacitance wiring line CL extending in almost parallel to thegate wiring lines (GL1 or GL2) is formed in an almost central areabetween the neighboring gate wiring lines. A metal pixel electrode SPMthat is connected to a second contact hole CNT2 of a TFT extends beneatha transparent pixel electrode SPT until the pixel center and curves tooverlap the hold capacitance wiring line CL and again extends under thetransparent pixel electrode SPT to thereby overlap a gate wiring lineGL2 at the next stage (shown in lower side of FIG. 8).

[0066] A cross-sectional structure which crosses between mutuallyneighboring drain wiring lines DL in the four transmissive areas betweenthe present stage gate wiring line GL1 (shown in upper side of FIG. 8)for TFT turn-on drive and the hold capacitance wiring line CL in theaforementioned arrangement and a sectional structure which crossesbetween neighboring drain wiring lines DL with respect to fourtransmissive areas of the hold capacitance CL and the next-stage gatewiring line GL2 are identically the same as the structures of theembodiment 1 shown in FIGS. 2 and 3, respectively. Accordingly in thisembodiment also, a potential variation occurring due to a strongelectric field which penetrates the TFT glass substrate from theleft-side drain wiring line DL1 to reach the neighboring metal pixelelectrode SPM in the areas of the present stage gate wiring line GL1 andhold capacitance wiring line CL is cancelled out by an electric fieldfrom the metal pixel electrode SPM from the right-side drain wiring lineDL2 in the area from the hold capacitance wiring line CL to thenext-stage gate wiring line GL2 to thereby make it possible to givestabilized display images without suffering from any crosstalk, inparticular in the dot-inversion drive method. The hold capacitancewiring line CL extends across the pixel center portion at which thetransparent pixel electrode SPT and common electrode wiring line CLT arecurved or bent to thereby provide an area in which liquid crystalmolecules rotate in the mutually opposite directions without anyappreciable decrease in aperture ratio. Furthermore, although the metalpixel electrode SPM also is cranked over the hold capacitance wiringline CL, this hardly acts as the factor that causes the aperture ratioto newly decrease.

[0067] An explanation will next be given of the role of a modificationcapacitance Cmod. In the plan view of FIG. 8 the TFT gate wiring linesGL are scanned in a line sequence fashion in the order of suffixes ofthe symbols shown in FIG. 8 in such a way that the transparent pixelelectrode SPT finally permits the transfer of an image signal voltage(pixel potential) from the left-side drain wiring line DL1. The metalpixel electrode has two major functions, one of which is for forming thehold capacitance used to stabilize the image quality by letting it bestacked with the hold capacitance wiring line CL, and the other of whichis to transfer the pixel potential toward the transparent pixelelectrode SPT through a third contact hole CNT3 over the holdcapacitance wiring line CL in the way stated previously. Thus, as far asthese functions are concerned, the metal pixel electrode SPM is nolonger required to extend up to a portion over the next-stage gatewiring line GL2. This is for preventing malfunction otherwise occurringdue to a pixel potential decrease under the influence of parasiticcapacitance components when the gate-on voltage of a TFT of the presentstage gate wiring line GL1 behaves to drop down at the turn-off (OFF)voltage.

[0068] When the gate-on voltage is applied to the TFT that is coupled tothe present stage gate wiring line GL1, an image voltage is applied tothe transparent pixel electrode SPT. On the other hand, it has beenknown among those skilled in the art that the pixel voltage decreases ata rate equivalent to the ratio of the hold capacitance with a TFTparasitic capacitance value to the liquid crystal capacitance wheneverthe gate-on voltage changes to the OFF voltage, resulting in a decreasein image quality. This may be suppressed by extremely enlarging thevalue of such a hold capacitance (called the storage capacitance, also)Cstg to be formed at a cross point between the metal pixel electrode SPMand hold capacitance wiring line CL. However, an aperture ratiodecreases.

[0069] The modification capacitance which is arranged at theintersection between the metal pixel electrode SPM that extends from thehold capacitance wiring line CL to the gate wiring line GL2 and the gatewiring line GL2 stabilizes the image quality by performing an operationwhich follows.

[0070] When the gate voltage on the stage gate wiring line GL1 changesfrom the OFF voltage to ON voltage, the TFT is driven to turn on causingthe pixel capacitance and hold capacitance Cstg to be charged up.Although in this case the pixel voltage potentially drops down in amoment that the voltage of gate wiring line GL1 on which the transparentpixel electrode SPT transfers an image voltage becomes equal to the OFFvoltage, letting the modification capacitance Cmod be set equal in valueto the TFT parasitic capacitance permits the next-stage gate wiring lineGL2 to change from the OFF voltage to ON voltage at the same time thatthe voltage of the present stage gate wiring line GL1 decreases inpotential whereby the pixel voltage is such that a potential increaseand decrease cancel out each other so that a stabilized operation isachievable without suffering from variations. In this way, it ispossible to provide the intended liquid crystal display device with anincreased aperture ratio while eliminating crosstalk, by specificallydesigning the metal pixel electrode SPM in such a way as to extend, fromthe present stage gate wiring line, at lower part of the transparentpixel electrode SPT adjacent to the left-side drain wiring line DL1,then cross the hold capacitance wiring line, next crank thereat, andagain extend beneath the transparent pixel electrode SPT adjacent to theright-side drain wiring line DL2, and then reach the next-stage gatewiring line GL2.

[0071]FIG. 9 shows a cross-section as taken along cut line 9-9′ of FIG.8. The left side of this drawing is a sectional view of a TFT, whereinan image voltage from drain wiring line DL is such that the p-typepolysilicon layer PSI(p) decreases in resistance upon application of theON voltage to the gate wiring line GL1 of a TFT, causing its potentialto be charged as a pixel potential to the liquid crystal capacitanceand/or hold capacitance Cstg. A lower electrode of the hold capacitanceCstg is a hold capacitance wiring line CL that is arranged by the sameprocess and the same material as those of gate wiring lines GL; itsupper electrode is a metal pixel electrode SPM which is connected to asecond contact hole CNT2 of the TFT. The transparent pixel electrode SPTis connected via a third contact hole CNT3 that is formed in organicprotective film FPAS and protective film PAS at a location above themetal pixel electrode SPM. A planar pattern is designed to have anH-like shape as shown in FIG. 8. The metal pixel electrode SPM furtherextends below the transparent pixel electrode SPT to reach thenext-stage gate wiring line GL2 and, here, is stacked with an interlayerdielectric film ILI sandwiched therebetween to thereby form amodification capacitance Cmod. The value of this modificationcapacitance Cmod is set at half of the capacitance of an inversion layerat the TFT's semiconductor layer PSI(p), for canceling of a variation ofthe pixel potential during line-sequential scanning of the ON and OFF ofthe gate voltage in the way stated above.

[0072] It is obvious that although each of the above-stated embodimentshas been explained under an assumption that the pixel electrodes are twoelectrodes, these may be replaced with three or more electrodes. Suchchanges and alterations are within the scope of the invention as far asthe principal concept of the invention is employed therein.

[0073] Additionally as apparent from FIG. 1, in the liquid crystaldisplay device having a first substrate and a second substrate which aredisposed to face each other with a liquid crystal layer interposedtherebetween and also having on or above the first substrate a pluralityof gate wiring lines and a plurality of drain wiring lines crossing theplurality of gate wiring lines in a matrix and thin-film transistorsformed at respective cross points or intersections of the gate wiringlines and drain wiring lines while letting a pixel being arranged by anarea that is surrounded by neighboring hate wiring lines and neighboringdrain wiring lines, it is desired that (a) a plurality of pixelelectrodes are provided, (b) at least two of the pixel electrodes have afirst region that is a linear portion with a two-layer structure ofupper and lower layers with a dielectric film sandwiched therebetweenand a second region that is a linear portion as provided only at theupper part of the dielectric film, (c) the above-mentioned two pixelelectrodes are different from each other in order of the first regionand the second region of the pixel electrodes, (d) portions which areformed at a lower layer of the dielectric film making up the firstregion are connected together at the two pixel electrodes, (e) thedistance between one pixel electrode of the two pixel electrodes and oneof two drain wiring lines which are disposed on the both sides of apixel is selected to be greater than twice the distance between it andthe other drain wiring line, and (f) the distance between the otherpixel electrode of the two pixel electrodes and the other of the twodrain wiring lines which are disposed on the both sides of the pixel isgreater than twice the distance between it and one drain wiring line.With such an arrangement, it becomes possible to more accuratelysuppress liquid crystals due to asymmetry, thus enabling achievement offurther reduction of crosstalk.

[0074] Also note that a pixel electrode of the two pixel electrodeswhich is arranged at a lower layer than the insulating film should notalways be made of metals and may alternatively be made of semiconductormaterials when the need arises. A reason of this is as follows. Lettingit have n+ type conductivity makes it possible to lower the resistanceto a degree sufficient for signal supplement within a single pixel and,therefore, semiconductor materials are treatable in a similar way tometals.

[0075] It has been described in detail that the use of the liquidcrystal display device of the type mainly employing TFTs and the IPSscheme in accordance with the present invention makes it possible toprovide a liquid crystal display device of high image quality withenhanced brightness and high display quality plus increased apertureratios while precluding any crosstalk.

What is claimed is:
 1. An active matrix type liquid crystal displaydevice having a first substrate and a second substrate which aredisposed to face each other with a liquid crystal layer interposedtherebetween and having above said first substrate a plurality of gatewiring lines and a plurality of drain wiring lines crossing saidplurality of gate wiring lines in a matrix form and also thin-filmtransistors formed in a way corresponding to respective cross points ofsaid gate wiring lines and said drain wiring lines, with a pixel beingconstituted by an area as surrounded by neighboring gate wiring linesand neighboring drain wiring lines, wherein a plurality of pixelelectrodes are provided, and at least two pixel electrodes thereof havea first area that is a linear portion constituted from two layers ofupper and lower layers with an insulating film sandwiched therebetweenand a second area that is a linear portion provided only at an upperportion of the insulating film, said two pixel electrodes are differentfrom each other in order of said first area and second area of saidpixel electrodes, and portions formed at a lower layer of saidinsulating film making up said first area are connected to each other atsaid two pixel electrodes.
 2. The active matrix type liquid crystaldisplay device according to claim 1, wherein a distance between onepixel electrode of said two pixel electrodes and one of two drain wiringlines disposed on both sides of a pixel is greater than twice a distancerelative to the other drain wiring line, whereas a distance between theother pixel electrode of said two pixel electrodes and the other drainwiring line of the two drain wiring lines disposed on the both sides ofthe pixel is greater than twice a distance relative to the one drainwiring line.
 3. The active matrix type liquid crystal display deviceaccording to claim 1, wherein said active matrix type liquid crystaldisplay device is of the lateral electric field type and has a pixelelectrode for forming a lateral electric field between it and any one ofsaid common electrodes formed above said first substrate or a commonwiring line.
 4. The active matrix type liquid crystal display deviceaccording to claim 3, wherein said two pixel electrodes extend up to theother gate wiring line at which the pixel electrodes are not connectedto TFTs to thereby form a hold capacitance together with the other gatewiring line with the insulating film therebetween.
 5. The active matrixtype liquid crystal display device according to claim 1, wherein saidpixel electrode and said common electrode are bent at an angle fallingwithin a range from about five (5) to twenty five (25) degrees in anarea for mutually connecting by said two pixel electrodes the portionsformed at lower layer of said insulating film making up said first area.6. The active matrix type liquid crystal display device according toclaim 1, wherein a common electrode wiring line extending insubstantially parallel to the gate wiring lines is formed in the areafor mutually connecting by said two pixel electrodes the portions formedat lower layer of said insulating film making up said first area, andwherein a wiring line for mutual connection of the portions formed atlower layer of said insulating film making up said first areaconstitutes a hold capacitance through said common electrode wiring lineand insulating film.
 7. The active matrix type liquid crystal displaydevice according to claim 1, wherein a pixel electrode of said two pixelelectrodes which is arranged at an upper layer than said insulating filmis formed of a transparent electrode.
 8. The active matrix type liquidcrystal display device according to claim 1, wherein a pixel electrodeof said two pixel electrodes which is arranged at a lower layer thansaid insulating film is formed of any one of a metal or a semiconductormaterial.